Однако прерывания где?
TimerIRQ не используется в сборке Zynq, а используется
только PrivateTimerIRQ* = 29
Что такое PrivateTimer? Он упомянут где-то, но сейчас не ищется в локальных ресурсах, включая документацию и исходники. Гуглим.
https://github.com/umanovskis/baremetal ... eduling.md
Всё классно, но у нас версия A7. Лезем в документ BCM2836-Cortex-A7-MPcore-Processor-Reference-Manual.pdfA Cortex-A9 MPCore CPU provides a global timer and private timers. There's one private timer per core. The global timer is constantly counting up, even with the CPU paused in debug mode. The per-core private timers count down from some starting value to zero, sending an interrupt when zero is reached. It's possible to use either timer for scheduling, but the typical solution is to use the private timer. It's somewhat easier to handle due to being 32 bits wide (the global timer is 64 bits) and due to stopping when the CPU is stopped.
Вот что там можно найти:
А также:Private Peripheral Interrupts
A PPI is an interrupt generated by a peripheral that is specific to a single
processor. There are seven PPIs for each CPU interface:
Legacy nFIQ signal (PPI0)
When the GIC interrupt bypass is in effect, such as after reset, the
external nFIQ signal bypasses the interrupt distributor logic and
directly drives the interrupt request to the corresponding processor.
When a processor uses the GIC rather than the external nFIQ signal,
by enabling its own CPU interface, the nFIQ signal is treated like
other interrupt lines and uses ID28. The interrupt is active-LOW
level-sensitive.
Secure Physical Timer event (PPI1)
This is the event generated from the Secure Physical Timer and uses
ID29. The interrupt is level-sensitive.
Non-secure Physical Timer event (PPI2)
This is the event generated from the Non-secure Physical Timer and
uses ID30. The interrupt is level-sensitive.
Legacy nIRQ signal (PPI3)
When the GIC interrupt bypass is in effect, such as after reset, the
external nIRQ signal bypasses the interrupt distributor logic and
directly drives the interrupt request to the corresponding processor.
When a processor uses the GIC rather than the external nIRQ signal,
by enabling its own CPU interface, the nIRQ signal is treated like
other interrupt lines and uses ID31. The interrupt is active-LOW
level-sensitive.
Virtual Timer event (PPI4)
This is the event generated from the Virtual Timer and uses ID27. The
interrupt is level-sensitive.
Hypervisor Timer event (PPI5)
This is the event generated from the Physical Timer in Hypervisor
mode and uses ID26. The interrupt is level-sensitive.
The Generic Timer can schedule events and trigger interrupts based on an incrementing counter
value. It provides:
• Generation of timer events as interrupt outputs.
• Generation of event streams.
• Support for Virtualization Extensions.
The Cortex-A7 MPCore Timer is compliant with the ARM Architecture Reference Manual.
This chapter only describes features that are specific to the Cortex-A7 MPCore implementation
The Cortex-A7 MPCore processor provides a set of four timers for each processor in the cluster.
• Physical Timer for use in Secure and Non-secure PL1 modes. The registers for the
Physical Timer are banked to provide Secure and Non-secure copies.
• Virtual Timer for use in Non-secure PL1 modes.
• Physical Timer for use in Hyp mode.
The counter value is distributed to the processor with a synchronous binary encoded 64-bit bus,
CNTVALUEB[63:0]